Tau Scaling Law: Huawei's Plan to Manufacture Better Chips

Transistors are nearing atomic scale limits and the semiconductor industry can no longer depend on Moore's Law to guide chip development.

The principle shaped the sector for more than 50 years, but now faces physical boundaries and economic challenges.

Huawei has introduced the Tau Scaling Law which aims to address these limitations. The principle shifts focus from transistor miniaturisation to reducing signal transmission times across chips and computing systems.

The company is developing technologies like LogicFolding based on this approach.

LogicFolding transitions chip architecture from traditional two-dimensional grids to three-dimensional layouts. The methodology creates a multi-level optimisation mechanism that spans semiconductor devices, circuits, chips and systems.

This could shorten data travel times and increase speed and energy efficiency.

He Tingbo, Co-President of Huawei, presented the development at the 2026 IEEE International Symposium on Circuits and Systems in Shanghai China. Peers and colleagues have named the principle Her's Law after He.

Three-dimensional chip architecture

The Tau (τ) Scaling Law represents a shift in semiconductor design philosophy. Huawei's LogicFolding methodology forms the core of this architectural approach.

Engineers previously designed microchips in two dimensions with components arranged across flat, grid-like planes. This layout forces signals to travel longer lateral distances.

LogicFolding breaks these physical boundaries by moving chip architecture to 3D design. The methodology layers multiple 2D planar circuits directly on top of each other rather than spreading components horizontally.

The mechanism functions like a multi-storey building where vertical movement between floors replaces horizontal travel. This stacking creates capacity for more transistors and positions core circuits closer together.

Transmission time between circuits serves as the primary indicator of frequency and performance.

The resistive and capacitive load of signal propagation drops when the logic layout is folded. This could unlock new dimensions of computational speed.

Time constant reduction strategy

The multi-level optimisation mechanism reduces the time constant τ at four layers of the technology stack.

Huawei says it is optimising resistance and parasitic capacitance of transistors and interconnects at the device level. This minimises the time constant τ at the underlying physical layer.

At the circuit level, the LogicFolding architecture shortens critical-path wiring and reduces the resistive and capacitive load of signal propagation.

At the chip level, Huawei employs coordinated design of software, architecture and silicon to achieve fine-grained, workload-driven control over instruction and data flows.

At the system level, the company is redefining interconnect protocols for computing systems with UnifiedBus. This aims to achieve unified memory addressing and native memory semantics for SuperPoDs.

Commercial applications

He discussed applications of the τ Scaling Law to smartphones and AI computing during the keynote speech. Over the past six years, Huawei has designed and mass-produced 381 chips based on the τ Scaling Law.

These chips serve a range of industries, sectors and markets.

The Kirin chips scheduled to launch in autumn 2026 will be the first to adopt the LogicFolding architecture. This commercial launch could enhance performance in consumer devices.

By 2031, the high-end chips that Huawei designs based on the τ Scaling Law are expected to feature transistor density equivalent to 14 Å processes. This represents a 1.4 nm scale.

Huawei says that it expects to work with scientists, engineers and industry partners worldwide to advance the electronics industry.